Method and apparatus for allowing phase conflicts in phase shifting mask and chromeless phase edges

ABSTRACT

Phase shifting layouts and masks with phase conflicts are described. The phase shifting layout defines light transmissive regions for use in defining selected features in a layer of material of an integrated circuit (IC). The phase shifting layout includes a phase conflict caused by two light transmissive regions that are out of phase with each other and which, without correction, would lead to the definition of an artifact in the layer of material. A corresponding mask adapted for use in conjunction with the phase shifting mask can ensure that the artifact is ultimately erased. The phase conflict is intentionally introduced into the phase shifting layout during phase assignment to permit all of the selected features to be defined using the phase shifting mask.

BACKGROUND

1. Field of the Invention

This invention relates to the field of semiconductor devices. More particularly, the invention relates to a method and apparatus for allowing phase conflicts between phase shifting regions in a phase shifting mask to be used in optical lithography processes for manufacturing integrated circuit devices.

2. Description of the Related Art

Semiconductor devices continue to be produced at reduced sizes as optical lithography processes have evolved. Techniques such as phase shifting have been developed to assist in the production of subwavelength features on the integrated circuits (IC) using optical lithography processes. Subwavelength features are features that are smaller than the wavelength of light used to create circuit patterns in the silicon. More generally, phase shifting can be used to create features smaller than a minimum realizable dimension for the given process.

Through the use of phase shifting masks, such subwavelength features can be efficiently produced. (Note, that the term “mask” as used in this specification is meant to include the term “reticle.”) One approach to producing a phase shifting mask (PSM) is to use destructive light interference caused by placing two, out of phase, light transmissive areas in close proximity in order to create an unexposed region on a photoresist layer of an IC. If that unexposed area is then protected from exposure when a binary mask is used to expose the remaining field (thus causing definition of the remaining structure), the resultant IC will include subwavelength features created by the PSM.

One approach to preparing an IC for production using PSMs is for one or more features of the IC to be identified for production using PSMs. For example, a designer might identify one or more particular features for production using the PSM, e.g. to define the identified gates (or other features) at subwavelength sizes.

A portion of a design layout 100 for a layer in an IC is shown in FIG. 1. Several distinct portions of the design layout are identified, particularly a gate 102 and a gate 104. In this example, both the gate 102 and the gate 104 are identified as “critical”, e.g. to be produced using a phase shifting mask.

A phase shifting mask 200 for defining the gate 102 and the gate 104 is shown in FIG. 2. The phase shifting mask 200 includes three light transmissive regions: a light transmissive region 202, a light transmissive region 204, and a light transmissive region 206. Light transmissive region 202 and light transmission region 204 are out of phase with one another, e.g. light through one is at phase 0 and the light through the other at phase π. Similarly, light transmissive region 204 and light transmissive region 206 are out of phase with one another, continuing the example if the light transmissive region 204 is at phase π, then the light transmissive region 206 would be at phase 0. These light transmissive regions are sometimes referred to both individually and collectively as phase shifters (the meaning will be apparent from usage). Additionally, the light transmissive regions are sometimes referred to as phase shifting areas. Note that between the light transmissive regions there is some protect (usually chrome) that assists in the definition of feature size and improves mask manufacturability.

FIG. 2 also illustrates that it is generally preferable to make the phase shifters (e.g. the light transmissive region 202, the light transmissive region 204, and the light transmissive region 206) relatively wide compared to the wavelength of the light (λ). For example, some phase shifting processes attempt to make the total width of the phase shifters and the protective area between them approximately 3λ. In this example, due to the proximity of the gates, instead of having two separate light transmissive regions between the gate 102 and the gate 104, a single light transmissive region, the light transmissive region 204 is used.

If two light transmissive regions were used for the light transmissive region 204, they would be assigned the same phase to prevent definition of an artifact on the IC. Similarly, if the light transmissive region 202 had to be of phase π and the light transmissive region 206 had to be of phase 0 (for example because of surrounding phase shifters, etc.), then a phase assignment problem would arise with respect to assigning phase to the light transmissive region 204. For example, if the phase assigned is 0 then, the gate 104 would not be successfully defined. Further splitting the light transmissive region 204 into two parts would produce an undesirable artifact on the IC.

Accordingly, what is needed is a method and apparatus for allowing phase assignment conflicts between phase shifting regions in a phase shifting mask. Additionally, both a phase shifting mask with phase assignment conflicts and a complimentary binary mask that can produce ICs with subwavelength structures is desired.

Frequently, phase shifting masks use chrome (or other protective materials) between edges of two phase shifters to improve mask manufacturability and critical dimension control. However, the requirement of a chrome (or other protective) edge on the phase shifting mask may make definition of certain densely packed features extremely difficult.

Accordingly, what is needed is a method and apparatus for allowing chromeless (or, more generally, protectless) phase transitions in a phase shifting mask. Additionally, both a phase shifting mask with chromeless phase transitions and a complimentary binary mask that can produce ICs with subwavelength structures is desired.

SUMMARY

Phase shifting layouts and masks with phase conflicts are described. The phase shifting layout defines light transmissive regions for use in defining selected features in a layer of material of an integrated circuit (IC). The selected features are sometimes referred to as critical features. The selected features are simply those features within a given layout, or portion of a layout, that a designer has specified would be desirable to produce using phase shifting. The selected features can then be produced at subwavelength sizes and can be more densely packed.

If the selected features are in relatively close proximity to one another, it may be difficult to assign phase to each of the light transmissive regions in the phase shifting layout. That is because the light transmissive regions on opposite sides of a given feature must be of opposite phase. Some IC layouts may have the selected features in an arrangement that makes it impossible to assign phase to the light transmissive regions so that the selected features can all be defined.

By adding a phase transition (and optionally control chrome) to subdivide one or more the light transmissive regions, it may then be possible to assign phase to all of the light transmissive regions so that all of the selected features are defined by the phase shifting mask. However, the added phase transition introduces a (intentional) conflict that if used, without correction, would lead to the definition of an artifact, or simply a structure, in the layer of material. This phase conflict is sometimes referred to as a false phase conflict since allowing it the layout data does not prevent the resultant mask from being used to successfully define the selected features.

A corresponding mask for use in conjunction with the phase shifting layout that includes the false conflict can also be defined. In one embodiment, a binary trim mask is used. The corresponding mask is characterized by the fact that when used in conjunction with the phase shifting mask, the artifact created by the false phase conflict will not be produced in the layer of material. If a binary trim mask is used, this can be accomplished by ensuring that there is an absence of protect (usually chrome) in the area of the trim mask corresponding to the location of the false phase conflict on the phase shifting mask.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a portion of a design layout for an integrated circuit (IC).

FIG. 2 illustrates a phase shifting mask to define the gates of the layout of FIG. 1.

FIG. 3 illustrates a phase shifting mask that includes a phase assignment conflict to define the gates of the layout of FIG. 1.

FIG. 4 illustrates a corresponding binary trim mask for the phase shifting mask of FIG. 3.

FIG. 5 is a process flow diagram for selectively allowing phase conflicts.

FIG. 6 illustrates a portion of a design layout for an IC overlaid with preliminary phase assignments and a phase conflict region.

FIG. 7 illustrates the layout of FIG. 6 overlaid with phase assignments after phase has been assigned to the phase conflict region.

FIG. 8 illustrates a portion of a design layout for an IC.

FIG. 9 illustrates a phase shifting layout for the layout of FIG. 8.

FIG. 10 illustrates a portion of a layer of material in an IC produced using a mask defined by the phase shifting layout of FIG. 9.

FIG. 11 illustrates a phase shifting layout for a portion of an IC.

DETAILED DESCRIPTION

Overview

Using embodiments of the invention, phase shifting masks that include certain phase conflicts (e.g. conflicts that, without further correction, would generate artifacts on the resultant IC) are selectively permitted. The result is that the phase assignment problem may be reduced in complexity because the problem can be further localized (introducing phase conflicts will break cycles that prevent coloring) and reduce the likelihood that the design must be redone.

First, the basic approach will be considered. Then, the selection process for permitting phase conflicts will be considered in greater detail. Finally, alternative embodiments of the invention will be described in greater detail.

Basic Approach

The basic approach is to introduce (or permit) phase transitions that would produce artifacts on the IC if not corrected. Turning to FIG. 3, an alternative phase shifting mask 300 for the gates of the layout 100 is shown. Assuming that the light transmissive region 202 and the light transmissive region are of phase 0 and π, respectively, a phase transition 310 can be introduced dividing the light transmissive region 206 of the phase shifting mask 200 into two separate light transmissive regions: the light transmissive region 304 and the light transmissive region 308. Further, the regions will be assign phase π and 0, respectively.

As noted, having the light transmissive region 304 and the light transmissive region 308 out of phase with one another will introduce an artifact between the two regions. Generally, this sort of transition would be unacceptable as part of phase assignment. However, the phase assignment rules are relaxed according to one embodiment of the invention to permit conflicts in areas where there is no structure in the layout, e.g. underneath the phase transition 310.

Also, note that in some embodiments, protect (usually chrome) can be placed between the light transmissive region 304 and the light transmissive region 308 to improve mask manufacturability and to better control the size of the resulting artifact (not shown).

FIG. 4 illustrates a corresponding binary trim mask 400 for use with the phase shifting mask 300 of FIG. 3. The binary trim mask 400 includes a protect 402 that prevents exposure of the structures in the layout 100. The protect 402 is oversized around the gates to protect the gates that were defined using the phase shifting mask 300. Notably, there is an absence of protect 404 (dotted region) where the artifact from the phase conflict on the phase shifting mask 300 would appear. The absence of protect 404 allows the artifact to become exposed, and thus removed during the processing of the layer of the IC. In some embodiments, an attenuated binary trim mask is used as the binary trim mask 400.

Now, a more detailed process flow used by some embodiments of the invention will be described.

Process Flow

The process will now be described in greater detail with reference to FIG. 5. This process can be used to localize resolution of phase assignments for phase shifting masks. Using this approach reduces the likelihood that layouts will need to be redesigned to accommodate definition of structures in a layer of an IC using phase shifting masks.

The process 500 starts at step 510 with preliminary phase assignments. For example, the layout 600 in FIG. 6 shows five gates inside an active region 602 (shown with dotted lines). Included in the layout 600 is a gate 604 and a gate 606. Preliminary phase assignments where phase shifters will be placed are superimposed on the layout 600 as “0” and “π”.

Next, at step 520, phase conflict regions can be identified. In FIG. 6, the preliminary assignment leaves a phase conflict region 612. If the phase conflict region 612 is assigned phase of 0 in a phase shifting mask then the gate 604 will not be defined by the phase shifting mask and similarly if assigned phase of π, the gate 606 will not be defined.

Also, the region 614 is shown since the assignment of phase to that region is not particularly important. In one embodiment, the region 614 will be opaque on the phase shifting mask. In another embodiment, the region 614 will be assigned a single phase, e.g. 0 or π. In a different embodiment, the region 614 may be subdivided into multiple regions with an assigned phase.

Then, at step 530, a determination is made as to whether the phase conflict regions, e.g. the phase conflict region 612, can be assigned phase by introducing a phase conflict. These added phase conflicts are sometimes referred to as “false” phase conflicts since the artifacts that they create can be wiped away. In some embodiments, the process will start at step 530 using input from another program that has performed preliminary phase assignment. False phase conflicts can be created by adding phase transitions to the (already placed) phase shifters. For example, FIG. 7 illustrates the layout 600 with a phase transition 710 added (shown as a dotted line). By adding the phase transition 710, the phase assignments can be changed and more particularly, the phase conflict region 612 can be assigned a phase. Also, note that adding the phase transition may cause the preliminary phase assignments to change. Cf. phase assignments of FIG. 6 and FIG. 7. For many standard cells, adding only a single extra phase transition will solve the phase assignment problem for a design.

In some instances, introduction of additional phase transitions may not be possible. For example, design rules, optical proximity limitations, mask manufacturability requirements, and/or other requirements may come into play. For example, in some embodiments, a minimum shifter width is 0.8λ for a λ=248 nm process. If this minimum width is used, then if the total width (or length) of the light transmissive region in the direction where the phase transition will be inserted is less than 1.6λ, then a phase transition cannot be inserted. Similarly, if the protect of the binary trim mask could not be fabricated so as to tolerate mask misalignment (over sizing of protect around critical features) while also allowing exposure of the artifact from the added phase conflict, then the additional phase transition cannot be added.

Finally, at step 540 the false phase conflict(s) identified at step 530 is/are added to the phase shifting mask and the corresponding binary mask is adjusted as well (not shown). As seen in FIG. 3 and FIG. 4, the phase shifting mask will include the extra phase transitions (with or without protect between the added phase transitions) and the binary mask will have an absence of protect over the regions where the artifact from the false phase transition appears.

For some layouts, there may be multiple false phase conflicts that could be introduced to solve a particular phase assignment problem. For example, layout 600 could be defined by placing the phase transition 710 in the corresponding location relative to the gate 606 or by adding more than one phase transition. Some embodiments of the invention attempt to introduce the minimum number of false phase conflicts necessary to make phase assignment possible.

Generally, phase transitions will be introduced by considering one or more of the following criteria: largest phase shifting region, phase shifting region having greatest process latitude, and ease of removal of artifacts created by the phase transition. Thus, in this example, the location of the phase transition 710 was in part selected over other possible locations because it had high process latitude, was relatively large, and easy to erase. The specific ranking of the selection criteria may be user controllable.

Accordingly a general approach for resolving phase assignment conflicts by introducing false phase conflicts has been described. The approach allows for highly localized solutions to phase assignment conflicts without the need to change the layout and/or define critical features without the use of phase shifting. (Recall that critical features are those features identified as to be produced using phase shifting, e.g. manually by the designer and/or in some sort of automated fashion.)

Chromeless Phase Transitions

The discussion in this section will refer to a phase transition boundary as being chromeless, in reference to current common mask fabrication technologies. More generally, the term chromeless in the context of this application refers to a phase shifting mask lacking a radiation/light protective region between the two (or more) light transmissive regions. The usage of the term will be apparent from the following discussion.

First some motivations for using the chromeless phase transitions will be discussed then some examples of the use of the same will be considered.

Specifically, the minimum allowable distance allowed between two shifters with opposite phase assignments is generally selected based on the minimum line width that is resolvable and inspectable on a mask. Presently, this is approximately 100 nm depending on the mask writer used. If however, the chromeless transitions (and phase conflicts) are positioned such that they will be cleared by the complimentary trim mask, the defects on the phase edge are not as important from an inspectability standpoint.

Further, in some embodiments, the chromeless phase transitions can be viewed as a method of further shrinking IC die size. Thus, more features, e.g. transistors, can be produced in a smaller area. This increases the number of chips per wafer and ultimately can provide significant cost savings/profit improvements. In one embodiment, the design rules for placing phase shifters are modified to eliminate the spacing requirement of 100 nm (or other distance depending on the particular process technology and mask writing equipment requirements) and thus more features can be defined using phase shifting masks and further those features can be more densely packed. Whether or not chromeless phase transitions are “preferred” vs. used only where needed may be user controllable depending on the configuration of the software defining the phase shifting layouts. However, as more fully described below, the chromeless approach may result in artifacts that cannot be easily removed using the binary trim mask,

Turning to FIG. 8, a portion of a layout for an IC is shown. The layout 800 includes three features, the feature 800, the feature 802 and the feature 804. The spacing between the top edge of the feature 802 (and the feature 804) and the bottom edge of the feature 800 is S. Recall, that in one embodiment, phase shifters are placed with a minimum width of 0.8λ, where λ is the wavelength of the light used. In discussing FIGS. 8-10 a λ=193 nm process technology will be considered. Returning to layout 800 in FIG. 8, if the amount of space, S, between the features is less than 0.8λ, 160 nm for our exemplary 193 nm process, then embodiments of the invention select not to define the feature 800 using phase shifting. However, if S=0.8λ, or is only slightly greater than it, there is the possibility of defining the feature using phase shifting, but there will be inadequate room for a protective chrome (which improves mask manufacturability and inspectability) between a phase shifter placed below the feature 800 and any phase shifters being used to define the feature 802 and the feature 804. Further, the close optical proximity may result in artifacts caused by phase conflicts to appear on the final IC.

Turning to FIG. 9 a proposed dark field phase shifting layout that uses chromeless phase transitions is shown (dark field of background not shaded for clarity). Specifically, FIG. 9 shows a layout 900 that has phase shifters 900, 902, 904, 906, and 908. The phase shifters are light transmissive regions designed to have the light shone through exit at a predetermined phase, e.g. 0 and π. The other elements of FIG. 9 are shown to assist in comprehension of the phase shifting layout. Specifically, the features 800, 802, and 804 are shown. In some embodiments, the bar composed of the mask substrate, a protective material such as chrome, of a narrower width than the features will separate the phase shifters (not shown). Note that in some embodiments the phase shifting layout will be fabricated as a dark field mask therefore there will be protective material by “default” between the phase shifters unless the phase shifters directly abut one another. Additionally, outlines for a trim mask are shown as solid lines around the features, trim mask outlines 910, 912, and 914. Lastly, two phase conflict areas are highlighted with dashed ovals, phase conflicts 916 and 920.

The phase conflict areas will result in additional structures being defined in the layer of material if the mask described by the layout is ultimately used without correction, e.g. by the corresponding binary trim mask. Further, some of those additional structures, or artifacts, are not possible to clear with the corresponding trim mask. Turning to FIG. 10 a portion of a layer of material in an IC produced using a mask defined by the phase shifting layout of FIG. 9 together with the corresponding binary trim mask. (Alternatively, FIG. 10 can represent the output of a suitable lithography simulation program.). The features produced by the phase shifting layout 900 together with the corresponding binary trim mask are shown as the features 1000, 1002, and 1004. The outline of the binary trim mask is shown as well as outlines 910, 912, and 914. Notably, because trim mask covered a portion of the phase conflict areas 916 and 920 (see FIG. 9), some artifacts remain on the finished IC, artifacts 1006 and 1008. The designer may have to decide for herself/himself if those artifacts are acceptable in the context of a particular design. In this case, the artifacts are acceptable and the IC can be used. If the resultant artifacts are unacceptable, then chromeless phase transitions cannot be used as shown for the layout 800. Some embodiments of the invention, include software capable of showing a simulation view or schematic view of the type shown in FIG. 10 to assist the designer in understanding the consequences of using a proposed phase shifting layout having chromeless phase transitions.

In some instances, the artifacts could be removed through more complex designs of the binary trim mask. However, such a complex design may itself be difficult to manufacture, interfere with the insertion of OPC features, and/or simply not provide sufficient benefit relative to the complexity and manufacturability problems created.

FIG. 11 shows a proposed phase shifting layout for a T-structure that uses chromeless phase transitions to define the T-structure. More specifically, FIG. 10 shows a layout 1000 including phase shifters 1104, 1106, 1108, and 1110. The original T-structure of the layout is shown as the feature 1102. The trim mask outline 1112 is also shown. Note however, that a phase conflict 1114 (shown as dashed oval) between the phase shifter 1104 and the phase shifter 1106 exists over the location of the chromeless phase transition.

Importantly, the distance between the edges of the trim mask outline 1112 in the area of the phase conflict 1114 need only be the minimum wafer resolvable space for the binary mask, S_(b). In one embodiment, for an exemplary λ=193 nm process, S_(b) might be 120 nm. Thus, it is possible to place phase shifters in close proximity, and without a phase transition, provided that the binary mask (through an absence of protect) can erase the artifacts of the chromeless phase transition in the area. This also highlights the fact that it in the circumstances where chromeless phase transitions are allowed, inspectability of the mask for defects at the edges of the transition is not important.

Alternative Embodiments

Although the discussion has focused on defining features using phase shifting masks it may also be desirable to also perform optical proximity correction (OPC) on the provided layout. More specifically, OPC in the context of a layout generally refers to the addition of subwavelength features such as hammerheads, endcaps, and serifs to a design. Returning to the layout 100 of FIG. 1. Light will diffract around the edges of protective areas of a mask. For example, in printed exposure of a binary mask for the layout 100, the top edge of the gate 102 might be shortened or pulled in. Adding OPC to the gate 102, e.g. a hammerhead, will allow the gate 102 to print more clearly. OPC can be integrated into the process 500 or can be separately performed. (Note, similar OPC could be performed for the gate 104.)

In some embodiments, defining gates at subwavelength sizes is referred to as “shrinking” gates. This colloquialism comes about because it reflects the size correspondence between regularly produced features and phase shifting mask-produced features.

Although the term “artifact” is used to refer to the structures that result from use of a phase shifting mask with false 0/180 conflicts (prior to erasure with a corresponding trim mask) other terms may be used as well. For example, the artifacts can also be consider non-structural areas, design violation areas (e.g. because they might fail a design rule check as too close, too tiny, etc), structures, artifacts of phase areas, and/or other suitable terms.

Embodiments of the invention can be used with deep ultraviolet (DUV), extreme ultraviolet (EUV), x-ray, and/or other lithography techniques. The particular mask substrate and protective areas should be adapted for the specific lithographic process.

The data structures and code described in this detailed description can be stored on a computer readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs) and DVDs (digital versatile discs or digital video discs), and computer instruction signals embodied in a transmission medium (with or without a carrier wave upon which the signals are modulated).

For example, the transmission medium may include a communications network, such as the Internet. In one embodiment, the computer readable storage medium includes one or more computer programs for identifying critical features, defining phase shifters for critical and/or preferred critical features, identifying conflicts between phase shifters and structures, selecting strategies for resolving conflicts, and/or resolving conflicts. In one embodiment, the electromagnetic waveform comprises computer programs accessed over a network, the computer programs for identifying critical features, defining phase shifters for critical and/or preferred critical features, identifying conflicts between phase shifters and structures, selecting strategies for resolving conflicts, and/or resolving conflicts.

In one embodiment, the electromagnetic waveform comprises computer data corresponding to a layout prepared according to the process 500. In one variation of this embodiment, the computer data is formatted according as one or more GDS-II data files. For example, the computer data could be the output of the process 500 being accessed across a network by mask data preparation software, e.g. CATS from Transcription Enterprises, Inc., a Numerical Technologies Company. In other embodiments, the electromagnetic waveform includes a computer program accessed across the network for selectively adding false phase conflicts to mask definitions for preparing layers of an integrated circuit.

The foregoing description of embodiments of the invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations will be apparent. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims. 

I claim:
 1. A method for producing phase shifting layout data from a portion of an integrated circuit (IC) layout, the method comprising: identifying a feature in the IC layout for definition with a phase shifting layout using a computer; generating the phase shifting layout data using the IC layout, the phase shifting layout data defining phase shifting areas in an opaque field for defining the feature in the material using a computer, the phase shifting layout adapted to be used in conjunction with a second layout data, the second layout data defining other structure in the material, and preventing erasure of the feature; determining using a computer if a conflict exists when assigning phase to phase shifting areas in the phase shifting layout data; and modifying the phase shifting layout data to resolve the conflict by inserting at least one chromeless phase transition in a phase shifting area of the phase shifting layout data.
 2. The method of claim 1, wherein the inserting the at least one chromeless phase transition further comprises subdividing a phase shifting area in the phase shifting layout data into a first phase shifting area and a second phase shifting area, the first and second phase shifting areas having different phase assignments.
 3. The method of claim 1, further comprising defining the second layout data such that the area exposed due to the inserting at least one chromeless phase transition will be exposed.
 4. The method of claim 1, wherein exposure of a layer of material using the phase shifting layout data without use of the second layout data will result in at least one artifact, the at least one artifact not present in the portion of the IC layout.
 5. A phase shifting mask for a portion of an integrated circuit (IC) layout comprising a plurality of features, the phase shifting mask comprising a plurality of light transmissive regions in an opaque field, each light transmissive region in the plurality of light transmissive regions permitting passage of light of a first wavelength at either a first phase or a second phase, and wherein the plurality of light transmissive regions includes a first light transmissive region and a second light transmissive region such that the plurality of light transmissive regions define the plurality of features in the IC layout; the first light transmissive region permits the passage of light at the first phase and the second light transmissive region permits the passage of light at the second phase; the first light transmissive region and the second light transmissive region have a shared boundary so as to cause destructive interference that would produce an artifact in a layer of material; and wherein a binary mask designed for use in conjunction with the phase shifting mask will prevent the artifact from remaining in a resultant integrated circuit.
 6. A dark field mask having phase areas for defining at least a portion of an integrated circuit (IC) layout, the phase areas being defined using the following process: defining phase regions in the dark field mask for use in defining structures of the IC layout; identifying a conflict preventing assignment of phase to the phase regions; inserting at least one false phase area directly abutting another phase area in the dark field mask to resolve the conflict; defining a corresponding trim mask to remove artifacts created by use of the dark field mask having the at least one false phase area.
 7. The dark field mask of claim 6, wherein due to the inserting, the dark field mask produces a false structure when used to expose a layer of material, the false structure not in the IC layout.
 8. The dark field mask of claim 6, wherein the false phase area comprises a non-structural phase area, the non-structural phase area acting in conjunction with the phase areas to produce at least one artifact when the dark field mask used to expose a layer of material.
 9. The dark field mask of claim 6, wherein the inserting further comprises at least one of selecting area with the highest process latitude, area the largest open region, and area where easiest to remove artifacts, for placement of the false phase area.
 10. An electromagnetic waveform, the electromagnetic waveform comprising a computer program for producing phase shifting layout data from a portion of an integrated circuit (IC) layout, the computer program further comprising: a first set of instructions for identifying a feature in the IC layout for definition with a phase shifting layout using a computer; a second set of instructions for generating the phase shifting layout data using the IC layout, the phase shifting layout data defining phase shifting areas in an opaque field for defining the feature in the material using a computer, the phase shifting layout adapted to be used in conjunction with a second layout data, the second layout data defining other structure in the material, and preventing erasure of the feature; a third set of instructions for determining using a computer if a conflict exists when assigning phase to phase shifting areas in the phase shifting layout data; and a fourth set of modifying the phase shifting layout data to resolve the conflict by inserting at least one chromeless phase transition in a phase shifting area of the phase shifting layout data.
 11. The electromagnetic waveform of claim 10, wherein the electromagnetic waveform comprises a computer program accessed over a network.
 12. The electromagnetic waveform of claim 10, wherein the computer program further comprises a fifth set of instructions for defining the second layout data.
 13. The electromagnetic waveform of claim 10, wherein the fourth set of instructions further comprises a set of instructions for selecting a location for the at least one chromeless phase transition using one or more of the following criteria: largest phase shifting region, phase shifting region having greatest process latitude, and ease of removal of artifacts created by the at least one chromeless phase transition using the second layout data.
 14. The electromagnetic waveform of claim 10, wherein the third set of instructions further comprises a fifth set of instructions for modeling phase assignment as a coloring problem and wherein a conflict exists if the coloring problem not solvable.
 15. The electromagnetic waveform of claim 14, wherein the fifth set of instructions further comprises a sixth set of instructions for modeling the coloring problem using a graph describing coloring dependencies and wherein the coloring problem not solvable if an odd length cycle exists in the graph.
 16. An apparatus for defining a dark field mask having phase areas for at least a portion of an integrated circuit (IC) layout, the apparatus comprising: means for defining phase regions in the dark field mask for use in defining structures of the IC layout; means for identifying a conflict preventing assignment of phase to the phase regions; means for inserting at least one false phase area directly abutting another phase area in the dark field mask to resolve the conflict; means for defining a corresponding trim mask to remove artifacts created by use of the dark field mask having the at least one false phase area.
 17. The apparatus of claim 16, wherein the means for identifying a conflict further comprises means for representing phase assignments as a coloring problem of assigning a color of either 0 or π to each phase area, and wherein a conflict is identified if the coloring problem not solvable.
 18. The apparatus of claim 16, wherein the means for defining a corresponding trim mask further comprises means for ensuring that area of the corresponding trim mask corresponding to location of artifacts produced by the dark field mask have an absence of protective material.
 19. The apparatus of claim 16, wherein the fourth means for inserting further comprises means for selecting a location for the at least one false phase area using one or more of the following criteria: largest phase shifting region, phase shifting region having greatest process latitude, and ease of removal of artifacts created by the at least one false phase area using the corresponding trim mask.
 20. The apparatus of claim 16, wherein the wherein artifacts created by use of the dark field mask comprise non-structural area created in a layer of material by use of the dark field mask.
 21. The apparatus of claim 16, wherein the wherein artifacts created by use of the dark field mask comprise design violation area created in a layer of material by use of the dark field mask.
 22. A method for producing phase shifting layout data from a portion of an integrated circuit (IC) layout, the method comprising: identifying a feature in the IC layout for definition with a phase shifting layout using a computer; generating the phase shifting layout data using the IC layout, the phase shifting layout data defining phase shifting areas in an opaque field for defining the feature in the material using a computer, the phase shifting layout adapted to be used in conjunction with a second layout data, the second layout data defining other structure in the material, and preventing erasure of the feature, and wherein there is a chromeless phase transition in the phase shifting layout data between a first and a second phase shifting area in the phase shifting layout data; and assigning phase to phase shifting areas in the phase shifting layout data while allowing phase assignment conflicts between the first and second phase shifting areas.
 23. The method of claim 22, wherein the chromeless phase transition corresponds to a phase transition where is an absence of protective material in the mask between the first and second phase shifting area.
 24. The method of claim 22, wherein usage of the phase shifting layout data in conjunction with the second layout data results in artifacts in the finished IC.
 25. The method of claim 22, wherein the first phase shifting area has a shifter width approximately equal to the minimum allowable shifter width.
 26. The method of claim 25, wherein minimum allowable shifter width is a predetermined multiple of the wavelength of light (λ).
 27. The method of claim 25, wherein minimum allowable shifter width is a 0.8 the wavelength of light (λ).
 28. The method of claim 22, wherein the chromeless phase transition position in an area where spacing between edges of trim in the corresponding second layout data approximately equal to minimum resolvable space for a binary mask.
 29. A method of phase shifting a layout, the method comprising: identifying a phase conflict caused by two sets of features interlaced within an active region of the layout, wherein placement of shifters for defining gate portions of the two sets of features generates a phase conflict; and resolving the phase conflict by dividing at least one shifter within the active region into at least two shifters with different phase.
 30. The method of claim 29, wherein resolving the phase conflict includes: determining an area of each shifter; and dividing the largest shifter.
 31. The method of claim 29, wherein resolving the phase conflict includes: determining a process latitude for each shifter; and dividing the shifter with the greatest process latitude.
 32. The method of claim 29, wherein resolving the phase conflict includes: determining ease of removal of an artifact caused by dividing each shifter; and dividing the shifter providing the greatest ease of removal.
 33. The method of claim 29, wherein the at least two shifters directly abut each other.
 34. The method of claim 29, wherein dividing the shifter includes providing a chromeless phase transition. 